Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx Virtex® FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
As multimedia applications, as well as communication systems, become more and more prevalent, there is an ever increasing need for systems to simultaneously handle data from multiple data sources. Examples of applications involving multiple data sources include: multi-camera security and surveillance systems, video/multimedia conferencing, multi-channel audio processing, and other various known types of multi-channel digital communications. Heretofore, there may have been one “decoder” for each data source. By use of the term “decoder” it should be understood that any of a variety of types of integrated circuits may be used. For example, the use of the term is decoder includes any of the following, as well as any combination of the following: sequencer, digital signal processor, and coder/decoder (“CODEC”). With respect to FPGAs, one or more of these integrate circuits may fully or partially be implemented in programmable logic.
Thus, for example, for a system where two data sources were communicating with one data user, the data user system would have two decoders to handle bitstreams from the two data sources. Notably, having multiple decoders associated with multiple data sources adds complexity to applications. Such applications, owing to use of multiple decoders, meant that factors such as operating flags, source-dependent constants, state variables, and dynamic register values, among other factors, made multiplexing data from multiple digital bitstreams relatively complex. For example, switching between input sources may involve well-defined complex state capture procedures for both front end parsing of data from multiple digital bitstreams and back end processing of such parsed information.
Accordingly, it would be desirable to provide a decoding architecture for instantiation in hardware, which may include at least in part programmable logic, capable of handling multiple digital bitstreams that reduces the complexity, and thus cost, associated with prior communication systems.